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VND7040AJ double channel high - side driver with multisense analog feedback for automotive applications datasheet - production data features max transient supply voltage v cc 40 v operating voltage range v cc 4 to 28 v typ. on - state resistance (per ch) r on 40 m current limitation (typ) i limh 34 a standby current (max) i stby 0.5 a ? automotive qualified ? general ? double channel smart high - side driver with multisense analog feedback ? very low standby current ? compatible with 3 v and 5 v cmos outputs ? multisense diagnostic functions ? multiplexed analog feedback of: load current with high precision proportional current mirror, v cc supply voltage and t chip device temperature ? overload and short t o ground (power limitation) indication ? thermal shutdown indication ? off - state open - load detection ? output short to v cc detection ? sense enable/disable ? protections ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? configurable latch - off on overtemperature or power limitation with dedicated fault reset pin ? loss of ground and loss of v cc ? reverse battery with external components ? electrostatic discharge protection applications ? all types of automotive resistive, inductive and capacitive loads ? specially intended for automotive signal lamps (up to p27w or sae1156 and r5w paralleled or led rear com binations) description the device is a double channel high - side driver manufactured using st proprietary vipower ? m0- 7 technology and housed in powersso - 16 package. the device is designed to drive 12 v automotive grounded loads through a 3 v and 5 v cmos - compatible interface, providing protection and diagnostics. the device integrates advanced protective functions such as load current limitation, overload active manageme nt by power limitation and overtemperature shutdown with configurable latch - off. a faultrst pin unlatches the output in case of fault or disables the latch - off functionality. a dedicated multifunction multiplexed analog output pin delivers s ophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to v cc and off - state open - load. a se nse enable pin allows off - state diagnosis to be disabled during the module low - power mode as well as external sense resistor sharing among similar devices. may 2015 docid027395 rev 1 1 / 46 this is information on a product in full production. www.st.com
contents VND7040AJ contents 1 block diagram and pin description ................................................ 5 2 electrical specification .................................................................... 7 2.1 absolute maximum ratings ................................................................ 7 2.2 thermal data ..................................................................................... 8 2.3 main electrical characteristics ........................................................... 8 2.4 waveforms ...................................................................................... 19 2.5 electrical characteristics curves ...................................................... 22 3 protections ..................................................................................... 26 3.1 power limitation ............................................................................... 26 3.2 thermal shutdown ........................................................................... 26 3.3 current limitation ............................................................................. 26 3.4 negative voltage clamp ................................................................... 26 4 application information ................................................................ 27 4.1 gnd protection network against reverse battery ............................. 27 4. 1.1 diode (dgnd) in the ground line ..................................................... 28 4.2 immunity against transient electrical disturbances .......................... 28 4.3 mcu i/os protection ........................................................................ 28 4.4 multisense - analog current sense .................................................. 29 4.4.1 principle of multisense signal generation ......................................... 30 4.4.2 tcase and vcc monitor ................................................................. 32 4.4.3 short to vcc and off - state open - load detection ........................... 33 5 maximum demagnetization energy (vcc = 16 v) ........................ 35 6 package and pcb thermal data .................................................... 36 6.1 powersso - 16 thermal data ............................................................ 36 7 package information ..................................................................... 39 7.1 powersso - 16 package information ................................................ 39 7.2 powersso - 16 packing information ................................................. 41 7.3 powersso - 16 m arking information ................................................. 43 8 order codes ................................................................................... 44 9 revision history ............................................................................ 45 2 / 46 docid027395 rev 1
VND7040AJ list of tables list of tables table 1: pin functions ................................................................................................................................. 5 table 2: suggested connection s for unused and not connected pins ........................................................ 6 table 3: absolute maximum ratings ........................................................................................................... 7 table 4: thermal data ................................................................................................................................. 8 table 5: power section ............................................................................................................................... 8 table 6: switching ....................................................................................................................................... 9 table 7: logic inputs ................................................................................................................................. 10 table 8: protections .................................................................................................................................. 11 table 9: multisense .................................................................................................................................. 11 table 10: truth table ................................................................................................................................. 18 table 11: multisense multiplexer addressing ........................................................................................... 19 table 12: iso 7637 - 2 - electrical transient conduction along supply line ................................................. 28 table 13: multisense pin levels in off - state .............................................................................................. 32 table 14: pcb properties ......................................................................................................................... 36 table 15: thermal parameters ................................................................................................................. 38 table 16: powersso - 16 mec hanical data ................................................................................................ 39 table 17: reel dimensions ....................................................................................................................... 41 table 18: powersso - 16 carrier tape dimensions .................................................................................... 42 table 19: device summary ....................................................................................................................... 44 table 20: document revision history ........................................................................................................ 45 docid027395 rev 1 3 / 46
list of figures VND7040AJ list of figures figure 1: block diagram .............................................................................................................................. 5 figure 2: configuration diagram (top view) ................................................................................................. 6 figure 3: current and voltage conventions ................................................................................................. 7 figure 4: iout/isense versus iout ....................................................................................................... 15 figure 5: current s ense accuracy versus iout ....................................................................................... 16 figure 6: switching time and pulse skew ................................................................................................. 16 figure 7: multisense timings (current sense mode) ................................................................................. 17 figure 8: multisense timings (chip temperature and vcc sense mode) .................................................. 17 figure 9: tdstkon .................................................................................................................................. 18 figure 10: latch functionality - behavior in hard short circuit condition (tamb << ttsd) ...................... 19 figure 11: latch functionality - behavior in hard short circuit condition .................................................... 20 figure 12 : latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 20 figure 13: standby mode activat ion ......................................................................................................... 21 figure 14: standby state diagram ............................................................................................................. 21 figure 15: off - state output current ......................................................................................................... 22 figure 16: standby current ....................................................................................................................... 22 figure 17: ignd(on) vs. iout ................................................................................................................... 22 figure 18: logic input high level voltage .................................................................................................. 22 figure 19: logic input low level voltage .................................................................................................... 22 figure 20: high level logic input current ................................................................................................... 22 figure 21: low level logic input current .................................................................................................... 23 figure 22: logic input hysteresis voltage ................................................................................................. 23 figure 23: faultrst input clamp voltage ................................................................................................. 23 figure 24: undervoltage shutdown ........................................................................................................... 23 figure 25: on - state resistance vs. tcase ................................................................................................. 23 figure 26 : on - state resistance vs. vcc ................................................................................................... 23 figure 27: turn - on voltage slope .............................................................................................................. 24 figure 28: turn - off voltage slope .............................................................................................................. 24 figure 29: won vs. tcase ......................................................................................................................... 24 figure 30: woff vs. tcase ......................................................................................................................... 24 figure 31: ilimh vs. tcase ....................................................................................................................... 24 figure 32: off - state open - l oad voltage detection threshold ................................................................... 24 figure 33: vsense clamp vs. tcase .......................................................................................................... 25 figure 34: vsenseh vs. tcase .................................................................................................................. 25 figure 35 : application diagram ................................................................................................................. 27 figure 36: simplified internal structure ..................................................................................................... 27 figure 37: multisense and diagnostic ? block diagram ............................................................................ 29 figure 38 : multisense block diagram ....................................................................................................... 30 figure 39: analogue hsd ? open - load detection in off - state ................................................................... 31 figure 40: open - load / short to vcc condition ......................................................................................... 32 figure 41: gnd voltage shift .................................................................................................................... 33 figure 42: maximum turn off current versus inductance .......................................................................... 35 figure 43: powersso - 16 on two - layers pcb (2s0p to jedec jesd 51 - 5) ............................................ 36 figure 44: powersso - 16 on four - layers pcb (2s2p to jedec jesd 51 - 7) ........................................... 36 figure 45: rthj - amb vs pcb copper area in open box free air condition (one channel on) ..................... 37 figure 46: powersso - 16 thermal impedance junction ambient single pulse (one channel on) .............. 37 figur e 47: thermal fitting model of a double - channel hsd in powersso - 16.......................................... 38 figure 48: powersso - 16 package outline ............................................................................................... 39 figure 49: powersso - 16 reel 13" ............................................................................................................ 41 figure 50: powersso - 16 carrier tape ...................................................................................................... 42 figure 51: powers so - 16 schematic drawing of leader and trailer tape .................................................. 42 figure 52: powersso - 16 marking information ......................................................................................... 43 4 / 46 docid027395 rev 1
VND7040AJ block diagram and pin de scription 1 block diagram and pin description figure 1 : block diagram table 1: pin functions name function v cc battery connection. output 0,1 power output. gnd ground connection. must be reverse battery protected by an external diode / resistor network. input 0,1 voltage controlled input pin with hysteresis, compatible with 3 v and 5 v cmos outputs. it controls output switch state. multisense multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. sen active high compatible with 3 v and 5 v cmos outputs pin; it enables the multisense diagnostic pin. sel 0,1 active high compatible with 3 v and 5 v cmos outputs pin; they address the multisense multiplexer. faultrst active low compatible with 3 v and 5 v cmos outputs pin; it unlatches the ou tput in case of fault; if kept low, sets the outputs in auto - restart. mode docid027395 rev 1 5 / 46
block diagram and pin description VND7040AJ figure 2 : configuration diagram (top view) table 2: suggested connections for unused and not connected pins connection / pin multisense n.c. output input sen, selx, faultrst floating not allowed x (1) x x x to ground through 1 k resistor x not allowed through 15 k resistor through 15 k resistor notes: (1) x: do not care. 6 / 46 docid027395 rev 1
VND7040AJ electrical specification 2 electrical specification figure 3 : current and voltage conventions v fn = v outn - v cc during reverse battery condition. 2.1 absolute maximum ratings stressing the device above the rating listed in table 3: "absolute maximum ratings" may cause permanent damage to the device. the se are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in table below for extended periods may affect device r eliability. table 3: absolute maximum ratings symbol parameter value unit v cc dc supply voltage 38 v -v cc reverse dc supply voltage 0.3 v ccpk maximum transient supply voltage (iso 16750 - 2:2010 test b clamped to 40v; r l = 4 ) 40 v v ccjs maximum jump start voltage for single pulse short circuit protection 28 v -i gnd dc reverse ground pin current 200 ma i out output 0,1 dc output current internally limited a -i out reverse dc output current 11 i in input 0,1 dc input current - 1 to 10 ma i sen sen dc input current i sel sel 0,1 dc input current i fr faultrst dc input current v fr faultrst dc input voltage 7.5 v v in output 0,1 multisense faultrst se n sel 0,1 input 0,1 i in i sel i sen i fr i gnd v sense v out v cc v fn i s i out i sense v cc v sel v sen v fr gapgcft00315 docid027395 rev 1 7 / 46
electrical specification VND7040AJ symbol parameter value unit i sense multisense pin dc output current (v gnd = v cc and v sense < 0 v) 10 ma multisense pin dc output current in reverse (v cc < 0 v) -20 e max maximum switching energy (single pulse) (t demag = 0.4 ms; t jstart = 150 c) 36 mj v esd electrostatic discharge (jedec 22a - 114f) ? input 0,1 ? multisense ? sen, sel 0,1 , faultrst ? output 0,1 ? v cc 4000 2000 4000 4000 4000 v v v v v v esd charge device model (cdm -aec - q100-011) 750 v t j junction operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 2.2 thermal data table 4: thermal data symbol parameter typ. value unit r thj - board thermal resistance junction - board (jedec jesd 51 - 5 / 51 - 8) (1) (2) 5.7 c/w r thj - amb thermal resistance junction - ambient (jedec jesd 51 - 5) (1) (3) 57 r thj - amb thermal resistance junction - ambient (jedec jesd 51 - 7) (1) (2) 23.5 notes: (1) one channel on. (2) devi ce mounted on four - layers 2s2p pcb (3) device mounted on two - layers 2s0p pcb with 2 cm 2 heatsink copper trace 2.3 main electrical characteristics 7 v < v cc < 28 v; - 40c < t j < 150c, unless otherwise specified. all typical values refer to v cc = 13 v; t j = 25c, unless otherwise specified. table 5: power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4 13 28 v v usd undervoltage shutdown 4 v v usdreset undervoltage shutdown reset 5 v v usdhyst undervoltage shutdown hysteresis 0.3 v r on on - state resistance (1) i out = 2.5 a; t j = 25c 40 m i out = 2.5 a; t j = 150c 80 i out = 2.5 a; v cc = 4 v; t j = 25c 60 8 / 46 docid027395 rev 1
VND7040AJ electrical sp ecification symbol parameter test conditions min. typ. max. unit v clamp clamp voltage i s = 20 ma; 25c < t j < 150c 41 46 52 v i s = 20 ma; t j = - 40c 38 v i stby supply current in standby at v cc = 13 v (2) v cc = 13 v; v in = v out = v fr = v sen = 0 v; v sel0,1 = 0 v; t j = 25c 0.5 a v cc = 13 v; v in = v out = v fr = v sen = 0 v; v sel0,1 = 0 v; t j = 85c (3) 0.5 v cc = 13 v; v in = v out = v fr = v sen = 0 v; v sel0,1 = 0 v; t j = 125c 3 t d_stby standby mode blanking time v cc = 13 v; v in = v out = v fr = v sel0,1 = 0 v; v sen = 5 v to 0 v 60 300 550 s i s(on) supply current v cc = 13 v; v sen = v fr = v sel0,1 = 0 v; v in0 = 5 v; v in1 = 5 v; i out0 = 0 a; i out1 = 0 a 5 8 ma i gnd(on) control stage current consumption in on state. all channels active. v cc = 13 v; v sen = 5 v; v fr = v sel0,1 = 0 v; v in0 = 5 v; v in1 = 5 v; i out0 = 2.5 a; i out1 = 2.5 a 12 ma i l(off) off - state output current at v cc = 13 v (2) v in = v out = 0 v; v cc = 13 v; t j = 25c 0 0.01 0.5 a v in = v out = 0 v; v cc = 13 v; t j = 125c 0 3 v f output - v cc diode voltage (2) i out = - 2.5 a; t j = 150c 0.7 v notes: (1) for each channel (2) powermos leakage included. (3) parameter specified by design; not subject to production test. table 6: switching v cc = 13 v; - 40c < t j < 150c, unless otherwise specified symbol parameter test conditions min. typ. max. unit t d(on) (1) turn -on delay time at t j = 25 c r l = 5.2 10 25 120 s t d(off) (1) turn - off delay time at t j = 25 c 10 40 100 (dv out /dt) on (1) turn - on voltage slope at t j = 25 c r l = 5.2 0.1 0.33 0.7 v/s (dv out /dt) off (1) turn - off voltage slope at t j = 25 c 0.1 0.35 0.7 w on switching energy losses at turn - on (t won ) r l = 5.2 ? 0.28 0.36 (2) mj w off switching energy losses at turn - off (t woff ) r l = 5.2 ? 0.26 0.36 (2) mj t skew (1) differential pulse skew (t phl - t plh ) r l = 5.2 -40 10 60 s notes: (1) see figure 6: "switching time and pulse skew" . (2) parameter guaranteed by design and characterization; not subject to production test. docid027395 rev 1 9 / 46
electrical specification VND7040AJ table 7: logic inputs 7 v < v cc < 28 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit input 0,1 characteristics v il input low level voltage 0.9 v i il low level input current v in = 0.9 v 1 a v ih input high level voltage 2.1 v i ih high level input current v in = 2.1 v 10 a v i(hyst) input hysteresis voltage 0.2 v v icl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 faultrst characteristics v frl input low level voltage 0.9 v i frl low level input current v in = 0.9 v 1 a v frh input high level voltage 2.1 v i frh high level input current v in = 2.1 v 10 a v fr(hyst) input hysteresis voltage 0.2 v v frcl input clamp voltage i in = 1 ma 5.3 7.5 v i in = -1 ma - 0.7 sel 0,1 characteristics (7 v < v cc < 18 v) v sell input low level voltage 0.9 v i sell low level input current v in = 0.9 v 1 a v selh input high level voltage 2.1 v i selh high level input current v in = 2.1 v 10 a v sel(hyst) input hysteresis voltage 0.2 v v selcl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 sen characteristics (7 v < v cc < 18 v) v senl input low level voltage 0.9 v i senl low level input current v in = 0.9 v 1 a v senh input high level voltage 2.1 v i senh high level input current v in = 2.1 v 10 a v sen(hyst) input hysteresis voltage 0.2 v v sencl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 10/ 46 docid027395 rev 1
VND7040AJ electrical specification table 8: protections 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit i limh dc short circuit current v cc = 13 v 24 34 48 a 4 v < v cc < 18 v (1) i liml short circuit current during thermal cycling v cc = 13 v; t r < t j < t tsd 13 t tsd shutdown temperature 150 175 200 c t r reset temperature (1) t rs + 1 t rs + 7 t rs thermal reset of fault diagnostic indication v fr = 0 v; v sen = 5 v 135 t hyst thermal hysteresis (t tsd - t r ) (1) 7 t j_sd dynamic temperature t j = - 40c; v cc = 13 v 60 k t latch_rst fault reset time for output unlatch (1) v fr = 5 v to 0 v; v sen = 5 v; ? e.g. ch 0 : v in0 = 5 v; v sel0 = 0 v; v sel1 = 0 v 3 10 20 s v demag turn - off output voltage clamp i out = 2 a; l = 6 mh; t j = - 40c v cc - 38 v i out = 2 a; l = 6 mh; t j = 25c to 150c v cc - 41 v cc - 46 v cc - 52 v v on output voltage drop limitation i out = 0.25 a 20 mv notes: (1) parameter guaranteed by design and characterization; not subject to production test. table 9: multisense 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit v sense_cl multisense clamp voltage v sen = 0 v; i sense = 1 ma -17 -12 v v sen = 0 v; i sense = -1 ma 7 current sense characteristics k ol i out /i sense i out = 0.01 a; v sense = 0.5 v; v sen = 5 v 530 dk cal /k cal (1) (2) current sense ratio drift at calibration point i out = 0.01 a to 0.05 a; i cal = 30 ma; v sense = 0.5 v; v sen = 5 v -30 30 % k led i out /i sense i out = 0.05 a; v sense = 0.5 v; v sen = 5 v 900 1700 2650 dk led /k led (1) (2) current sense ratio drift i out = 0.05 a; v sense = 0.5 v; v sen = 5 v -25 25 % docid027395 rev 1 11/ 46
electrical specification VND7040AJ 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit k 0 i out /i sense i out = 0.25 a; v sense = 0.5 v; v sen = 5 v 940 1600 2200 dk 0 /k 0 (1) (2) current sense ratio drift i out = 0.25 a; v sense = 0.5 v; v sen = 5 v -20 20 % k 1 i out /i sense i out = 0.5 a; v sense = 4 v; v sen = 5 v 1060 1500 1970 dk 1 /k 1 (1) (2) current sense ratio drift i out = 0.5 a; v sense = 4 v; v sen = 5 v -15 15 % k 2 i out /i sense i out = 1.5 a; v sense = 4 v; v sen = 5 v 1140 1410 1710 dk 2 /k 2 (1) (2) current sense ratio drift i out = 1.5 a; v sense = 4 v; v sen = 5 v -10 10 % k 3 i out /i sense i out = 4.5 a; v sense = 4 v; v sen = 5 v 1260 1400 1540 dk 3 /k 3 (1) (2) current sense ratio drift i out = 4.5 a; v sense = 4 v; v sen = 5 v -5 5 % i sense0 multisense leakage current multisense disabled: v sen = 0 v 0 0.5 a multisense disabled: -1 v < v sense < 5 v (1) - 0.5 0.5 multisense enabled: v sen = 5 v; all channels on; i outx = 0 a; ch x diagnostic selected; ? e.g. ch 0 : v in0 = 5 v; v in1 = 5 v; v sel0 = 0 v; v sel1 = 0 v; i out0 = 0 a; i out1 = 2.5 a 0 2 multisense enabled: v sen = 5 v; ch x off; ch x diagnostic selected: ? e.g. ch 0 : v in0 = 0 v; v in1 = 5 v; v sel0 = 0 v; v sel1 = 0 v; i out1 = 2.5 a 0 2 v out_msd (1) output voltage for multisense shutdown v sen = 5 v; r sense = 2.7 k; ? e.g. ch 0 : v in0 = 5 v; v sel0 = 0 v; v sel1 = 0 v; i out0 = 2.5 a 5 v v sense_sat multisense saturation voltage v cc = 7 v; r sense = 2.7 k; v sen = 5 v; v in0 = 5 v; v sel0 = 0 v; v sel1 = 0 v; i out0 = 4.5 a; t j = 150c 5 v i sense_sat (1) cs saturation current v cc = 7 v; v sense = 4 v; v in0 = 5 v; v sen = 5 v; v sel0 = 0 v; v sel1 = 0 v; t j = 150c 4 ma 12/ 46 docid027395 rev 1
VND7040AJ electrical spec ification 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit i out_sat (1) output saturation current v cc = 7 v; v sense = 4 v; v in0 = 5 v; v sen = 5 v; v sel0 = 0 v; v sel 1 = 0 v; t j = 150c 6 a off - state diagnostic v ol off - state open- load voltage detection threshold v sen = 5 v; ch x off; ch x diagnostic selected ? e.g: ch 0 v in0 = 0 v; v sel0 = 0 v; v sel1 = 0 v 2 3 4 v i l(off2) off - state output sink current v in = 0 v; v out = v ol ; t j = - 40c to 125c -100 -15 a t dstkon off - state diagnostic delay time from falling edge of input (see figure 9: "tdstkon" ) v sen = 5 v; ch x on to off transition; ch x diagnostic selected ? e.g: ch 0 v in0 = 5 v to 0 v; v sel0 = 0 v; v sel1 = 0 v; i out0 = 0 a; v out = 4 v 100 350 700 s t d_ol_v settling time for valid off - state open load diagnostic indication from rising edge of sen v in0 = 0 v; v in1 = 0 v; v fr = 0 v; v sel0 = 0 v; v sel1 = 0 v; v out0 = 4 v; v sen = 0 v to 5 v 60 s t d_vol off - state diagnostic delay time from rising edge of v out v sen = 5 v; ch x off; ch x diagnostic selected ? e.g: ch 0 v in0 = 0 v; v sel0 = 0 v; v sel1 = 0 v; v out = 0 v to 4 v 5 30 s chip temperature analog feedback v sense_tc multisense output voltage proportional to chip temperature v sen = 5 v; v sel0 = 0 v; v sel1 = 5 v; v in0,1 = 0 v; r sense = 1 k; t j = - 40c 2.325 2.41 2.495 v v sen = 5 v; v sel0 = 0 v; v sel1 = 5 v; v in0,1 = 0 v; r sense = 1 k; t j = 25c 1.985 2.07 2.155 v v sen = 5 v; v sel0 = 0 v; v sel1 = 5 v; v in0,1 = 0 v; r sense = 1 k; t j = 125c 1.435 1.52 1.605 v dv sense_tc /dt temperature coefficient t j = - 40c to 150c - 5.5 mv/ k transfer function v sense_tc (t) = v sense_tc (t 0 ) + dv sense_tc / dt * (t - t 0 ) v cc supply voltage analog feedback v sense_vcc multisense output voltage proportional to v cc supply voltage v cc = 13 v; v sen = 5 v; v sel0 = 5 v; v sel1 = 5 v; v in0,1 = 0 v; r sense = 1 k 3.16 3.23 3.3 v docid027395 rev 1 13/ 46
electrical specification VND7040AJ 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit transfer function (3) v sense_vcc = v cc / 4 fault diagnostic feedback (see table 10: "truth table" ) v senseh multisense output voltage in fault condition v cc = 13 v; r sense = 1 k; ? e.g: ch 0 in open load v in0 = 0 v; v sen = 5 v; v sel0 = 0 v; v sel1 = 0 v; i out0 = 0 a; v out = 4 v 5 6.6 v i senseh multisense output current in fault condition v cc = 13 v; v sense = 5 v 7 20 30 ma multisense timings (current sense mode - see figure 7: "multisense timings (current sense mode)" ) (4) t dsense1h current sense settling time from rising edge of sen v in = 5 v; v sen = 0 v to 5 v; r sense = 1 k; r l = 5.2 60 s t dsense1l current sense disable delay time from falling edge of sen v in = 5 v; v sen = 5 v to 0 v; r sense = 1 k; r l = 5.2 5 20 s t dsense2h current sense settling time from rising edge of input v in = 0 v to 5 v; v sen = 5 v; r sense = 1 k; r l = 5.2 100 250 s t dsense2h current sense settling time from rising edge of i out (dyna mic response to a step change of i out ) v in = 5 v; v sen = 5 v; r sense = 1 k; i sense = 90 % of i sensemax ; r l = 5.2 100 s t dsense2l current sense turn - off delay time from falling edge of input v in = 5 v to 0 v; v sen = 5 v; r sense = 1 k; r l = 5.2 50 250 s multisense timings (chip temperature sense mode - see figure 8: "multisense timings (chip temperature and vcc sense mode)" ) (4) t dsense3h v sense_tc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0 = 0 v; v sel1 = 5 v; r sense = 1 k 60 s t dsense3l v sense_tc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0 = 0 v; v sel1 = 5 v; r sense = 1 k 20 s multisense timings (v cc voltage sense mode - see figure 8: "multisense timings (chip temperature and vcc sense mode)" ) (4) t dsense4h v sense_vcc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0 = 5 v; v sel1 = 5 v; r sense = 1 k 60 s t dsense4l v sense_vcc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0 = 5 v; v sel1 = 5 v; r sense = 1 k 20 s multisense timings (multiplexer transition times) (4) t d_xtoy multisense transition delay from ch x to ch y v in0 = 5 v; v in1 = 5 v; v sen = 5 v; v sel1 = 0 v; v sel0 = 0 v to 5 v; i out0 = 0 a; i out1 = 3 a; r sense = 1 k 20 s 14/ 46 docid027395 rev 1
VND7040AJ electrical specification 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit t d_cstotc multisense transition delay from current sense to t c sense v in0 = 5 v; v sen = 5 v; v sel0 = 0 v; v sel1 = 0 v to 5 v; i out0 = 1.5 a; r sense = 1 k 60 s t d_tctocs multisense transition delay from t c sense to current sense v in0 = 5 v; v sen = 5 v; v sel0 = 0 v; v sel1 = 5 v to 0 v; i out0 = 1.5 a; r sense = 1 k 20 s t d_cstovcc multisense transition delay from current sense to v cc sense v in1 = 5 v; v sen = 5 v; v sel0 = 5 v; v sel1 = 0 v to 5 v; i out1 = 1.5a; r sense = 1 k 60 s t d_vcctocs multisense transition delay from v cc sense to current sense v in1 = 5 v; v sen = 5 v; v sel0 = 5 v; v sel1 = 5 v to 0 v; i out1 = 1.5 a; r sense = 1 k 20 s t d_tctovcc multisense transition delay from t c sense to v cc sense v cc = 13 v; t j = 125c; v sen = 5 v; v sel0 = 0 v to 5 v; v sel1 = 5 v; r sense = 1 k 20 s t d_vcctotc multisense transition delay from v cc sense to t c sense v cc = 13 v; t j = 125c; v sen = 5 v; v sel0 = 5 v to 0 v; v sel1 = 5 v; r sense = 1 k 20 s t d_cstovsenseh multisense transition delay from stable current sense on ch x to v senseh on ch y v in0 = 5 v; v in1 = 0 v; v sen = 5 v; v sel1 = 0 v; v sel0 = 0 v to 5 v; i out0 = 3 a; v out1 = 4 v; r sense = 1 k 20 s notes: (1) parameter guaranteed by design and characterization; not subject to production test. (2) all values refer to v cc = 13 v; t j = 25c, unless otherwise specified. (3) v cc sensing an d t c sensing are referred to gnd potential. (4) transition delay are measured up to +/ - 10% of final conditions. figure 4 : iout/isense versus iout gapgcft01328 0 5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 3 0 0 0 0 1 2 3 4 5 k - f a c t o r i o u t [ a ] m a x min t y p oc0235 e 1 15 46
electrical specification VND7040AJ figure 5 : current sense accuracy versus iout figure 6 : switching time and pulse skew gapgcft01329 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 0 1 2 3 4 5 % i o u t [ a ] c u rr e n t s e n s e un c a li b r a t e d p r e c i s i o n c u rr e n t s e n s e c a li b r a t e d p r e c i s i o n t t cc ton 0 cc 20 cc to t td on tp tp td o t d t dt d t dt gapg2609141134cft 16 46 oci027395 re 1
VND7040AJ electrical spec ification figure 7 : multisense timings (current sense mode) figure 8 : multisense timings (chip temperature and vcc sense mode) curr e n t se n se in1 se n i o u t 1 t d se n se 2 h t d se n se 1 l t d se n se 2 l t d se n se 1 h se l0 se l1 lo w h i g h lo w h i g h lo w h i g h gapgcft00318 se n se se n v c c t se n se 4 t se n se 4 l t se n se 3 l t se n se 3 se l0 se l1 lo w i g lo w i g lo w i g v sens e v sense vc c v sens e v sense t c v cc vo l t a ge se n se m o d e ch i p t e m pe r a tur e se n se m o d e gapgcft00319 oci027395 re 1 17 46
electrical specification VND7040AJ figure 9 : tdstkon table 10: truth table mode conditions in x fr sen sel x out x multisense comments standby all logic inputs low l l l l l hi -z low quiescent current consumption normal nominal load connected; t j < 150 c l x see (1) l see (1) h l h see (1) outputs configured for auto - restart h h h see (1) outputs configured for latch - off overload overload or short to gnd causing: t j > t tsd or t j > t j_sd l x see (1) l see (1) h l h see (1) output cycles with temperature hysteresis h h l see (1) output latches - off undervoltage v cc < v usd (falling) x x x x l l hi -z hi -z re - start when v cc > v usd + v usdhyst (rising) off - state diagnostics short to v cc l x see (1) h see (1) open - load l x h see (1) external pull - up negative output voltage inductive loads turn - off l x see (1) < 0 v see (1) notes: (1) refer to table 11: "multisense multiplexer addressing" t dstkon v inpu t v ou t multisense v ou t > v o l gapg260914 1 140cf t 18/ 46 docid027395 rev 1
VND7040AJ electrical specification table 11: multisense multiplexer addressing sen sel 1 sel 0 mux channel multisense output normal mode overload off - state diag. (1) negative output l x x hi -z h l l channel 0 diagnostic i sense = 1/k * i out0 v sense = v senseh v sense = v senseh hi -z h l h channel 1 diagnostic i sense = 1/k * i out1 v sense = v senseh v sense = v senseh hi -z h h l t chip sense v sense = v sense_tc h h h v cc sense v sense = v sense_vcc notes: (1) in case the output channel corresponding to the selected mux channel is latched off while the relevant input is low, multisense pin delivers feedback according to off - state diagnostic. example 1: fr = 1; in 0 = 0; out 0 = l (latched); mux channel = channel 0 diagnostic; mutisense = 0. example 2: fr = 1; in 0 = 0; out 0 = latched, v out0 > v ol ; mux channel = channel 0 diagnostic; mutisense = v senseh 2.4 waveforms figure 10 : latch functionality - behavior in hard short circuit condition (tamb << ttsd) docid027395 rev 1 19/ 46
electrical specification VND7040AJ figure 11 : latch functionality - behavior in hard short circuit condition figure 12 : latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 20/ 46 docid027395 rev 1
VND7040AJ electrical spec ification figure 13 : standby mode activation figure 14 : standby state diagram docid027395 rev 1 21/ 46
electrical specification VND7040AJ 2.5 electrical characteristics curves figure 15 : off - state output current figure 16 : standby current figure 17 : ignd(on) vs. iout figure 18 : logic input high level voltage figure 19 : logic input low level voltage figure 20 : high level logic input current 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] il o ff [ n a ] o ff s t a t e v cc = 13 v v i n = v ou t = 0 gapgcft01308 gapgcft01309 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] i s t b y [ a ] v cc = 13 v gapgcft01310 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] i g nd ( o n ) [ m a ] v cc = 13 v i ou t0 = i ou t1 = 2 . 5 a gapgcft01311 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 1 . 6 1 . 8 2 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] v i h , v f rh , vse l h , vse n h [ v ] gapgcft01312 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] v il l v f r l , vse l l , vse n l [ v ] gapgcft01313 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] ii h , i f rh , i se l h , i se n h [ a ] 22/ 46 docid027395 rev 1
VND7040AJ electrical specification figure 21 : low level logic input current figure 22 : logic input hysteresis voltage figure 23 : faultrst input clamp voltage figure 24 : undervoltage shutdown figure 25 : on - state resistance vs. tcase figure 26 : on - state resistance vs. vcc gapgcft01314 0 0. 5 1 1. 5 2 2. 5 3 3. 5 4 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] ii l , i f r l , i se l l , i se n l [ a ] gapgcft01315 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] v i ( h y st) , v f r ( h y st) , vse l ( h y st) , vse n ( h y st) [ v ] gapgcft01316 - 1 0 1 2 3 4 5 6 7 8 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] v f rc l [ v ] ii n = 1 m a ii n = - 1 m a gapgcft01317 0 1 2 3 4 5 6 7 8 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] v u s d [ v ] gapgcft01318 0 10 20 30 40 50 60 70 80 90 10 0 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] r on [ m o h m ] i ou t = 2. 5a v cc = 13 v gapgcft01319 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 v cc [v] r on [ m o h m ] t = - 4 0 c t = 2 5 c t = 12 5 c t = 15 0 c docid027395 rev 1 23/ 46
electrical specification VND7040AJ figure 27 : turn - on voltage slope figure 28 : turn - off voltage slope figure 29 : won vs. tcase figure 30 : woff vs. tcase figure 31 : ilimh vs. tcase figure 32 : off - state open - load voltage detection threshold gapgcft01320 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0. 8 0. 9 1 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] ( d v ou t / d t) o n [ v / s] v cc = 13 v r l = 5. 2 t [ c ] ( d v ou t / d t) o ff [ v / s] v cc = 13 v r l = 5. 2 gapgcft01321 gapgcft01322 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] w on [ m j ] gapgcft01323 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] w o ff [ m j ] gapgcft01324 10 15 20 25 30 35 40 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] ili m h [ a ] v cc = 13 v 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] v o l [ v ] gapgcft01325 24 46 oci027395 re 1
VND7040AJ electrical specification figure 33 : vsense clamp vs. tcase figure 34 : vsenseh vs. tcase gapgcft01326 - 1 0 1 2 3 4 5 6 7 8 9 10 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] vse n se _c l [ v ] ii n = 1m a ii n = - 1m a gapgcft01327 0 1 2 3 4 5 6 7 8 9 10 - 50 - 25 0 25 50 75 10 0 12 5 15 0 17 5 t [ c ] vse n se h [ v ] docid027395 rev 1 25/ 46
protections VND7040AJ 3 protections 3.1 power limitation the basic working principle of this protection consists of an indirect measurement of the junction temperatur e swing t j through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output mosfet as soon as t j exceeds the safety level of t j_sd . according to the voltage level on the faultrst pin, the output mosfet switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (faultrst = low) or remains off (faultrst = high). the protection prevents fast thermal transient effects and, consequentl y, reduces thermo - mechanical fatigue. 3.2 thermal shutdown in case the junction temperature of the device exceeds the maximum allowed threshold (typically 175c), it au tomatically switches off and the diagnostic indication is triggered. according to the voltage level on the faultrst pin, the device switches on again as soon as its junction temperature drops to t r (faultrst = low) or remains off (faultrst = high). 3.3 current limitation the device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. consequently, in case of short circuit, overload or during load power - up, the output current is clamped to a safety level, i limh , by operating the output power mosfet in the activ e region. 3.4 negative voltage clamp in case the device drives inductive load, the output voltage reaches a negative value during turn off. a negative voltage cla mp structure limits the maximum negative voltage to a certain value, v demag , allowing the inductor energy to be dissipated without damaging the device. 26/ 46 docid027395 rev 1
VND7040AJ application information 4 application information figure 35 : application diagram 4.1 gnd protection network against reverse battery figure 36 : simplified internal structure docid027395 rev 1 27/ 46
application information VND7040AJ 4.1.1 diode (dgnd) in the ground line a resistor (typ. r gnd = 4.7 k ) should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network produces a shift (600 mv) in the input thre shold and in the status output values if the microprocessor ground is not common to the device ground. this shift does not vary if more than one hsd shares the same diode/resistor network. 4.2 immunity against transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in acco rdance with iso7637 - 2:2011 (e) and iso 16750 - 2:2010. the related function performance status classification is shown in table 12: "iso 7637 - 2 - electrical transient conduction along supply line" . test pulses are applied dir ectly to dut (device under test) both in on and off - state and in accordance to iso 7637 - 2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. status ii is defined in iso 7637 - 1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. table 12: iso 7637 -2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator internal impedance level u s (1) min max 1 iii -112v 500 pulses 0,5 s 2ms, 10 2a iii +55v 500 pulses 0,2 s 5 s 50s, 2 3a iv -220v 1h 90 ms 100 ms 0.1s, 50 3b iv +150v 1h 90 ms 100 ms 0.1s, 50 4 (2) iv -7v 1 pulse 100ms, 0.01 load dump according to iso 16750 - 2:2010 test b (3) 40v 5 pulse 1 min 400ms, 2 notes: (1) u s is the peak amplitude as defined for each test pulse in iso 7637 - 2:2011(e), chapter 5.6. (2) test pulse from iso 7637 - 2:2004(e). (3) with 40 v external suppressor referred to ground ( - 40c < t j < 150c). 4.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line both to prevent the microcontroller i/o pins to latch - up and to protect the hsd inputs. 28/ 46 docid027395 rev 1
VND7040AJ application information the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch - up limit of microcontroller i/os. equation v ccpeak /i latchup r prot (v ohc - v ih - v gnd ) / i ihma x calculation example: for v ccpeak = - 150 v; i latchup 20 ma; v ohc 4.5 v 7.5 k r prot 140 k. recommended values: r prot = 15 k 4.4 multisense - analog current sense diagnostic information on device and load status are provided by an analog output pin (multisense) delivering the following signals: ? current monitor: current mirror of channel output current ? v cc monitor: voltage propotional to v cc ? t case : voltage propotional to chip temperature those signals are routed through an analog multiplexer which is configured and controlled by means of selx and sen pins, according to the address map in multisense multiplexer addressing table . figure 37 : multisense and diagnostic ? block diagram docid027395 rev 1 29/ 46
application information VND7040AJ 4.4.1 principle of multisense signal generation figure 38 : multisense block diagram current monitor when current mode is selected in the multisense, this output is capable to provide: ? current mirror proportional to the load current in normal operation, delivering current proportional to the load according to kno wn ratio named k ? diagnostics flag in fault conditions delivering fixed voltage v senseh the current delivered by the current sense circuit, i sense , can be easily converted to a voltage v sense by using an external sense resistor, r sense , allowing continuous load monitoring and abnormal condition detection. normal operation (channel on, no fault, sen active) while device is operating in normal conditions (no fault intervention), v sense calculation can be done using simple equations current provided by multisen se output: i sense = i out /k voltage on r sense : v sense = r sense i sense = r sense i out /k where: ? v sense is voltage measurable on r sense resistor ? i sense is current provided from multisense pin in current output mode 30/ 46 docid027395 rev 1
VND7040AJ application information ? i out is current flowing through output ? k factor represents the ratio between powermos cells and sensemos cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between i out and i sense . failure flag indication in case of power limitation/overtemperature, the fault is indicated by the multisense pin which is switched to a ?current limited? voltage source, v senseh . in any case, the current sourced by the multisense in this condition is limited to i sense h . the typical behavior in case of overload or hard short circuit is shown in waveforms section . figure 39 : analogue hsd ? open - load detection in off - state docid027395 rev 1 31/ 46
application information VND7040AJ figure 40 : open - load / short to vcc condition table 13: multisense pin levels in off - state condition output multisense sen open - load v out > v ol hi -z l v senseh h v out < v ol hi -z l 0 h short to v cc v out > v ol hi -z l v senseh h nominal v out < v ol hi -z l 0 h 4.4.2 tcase and vcc monitor in this case, multisense output operates in voltage mode and output level is referred to device g nd. care must be taken in case a gnd network protection is used, because of a voltage shift is generated between device gnd and the microcontroller input gnd reference. figure 41: "gnd voltage shift" shows link between v mea sured and real v sense signal. 32/ 46 docid027395 rev 1
VND7040AJ application information figure 41 : gnd voltage shift v cc monitor battery monitoring channel provides v sense = v cc / 4. case temperature monitor case temperature monitor is capable to provide information about the actual dev ice temperature. since a diode is used for temperature sensing, the following equation describes the link between temperature and output v sense level: v sense_tc (t) = v sense_tc (t 0 ) + dv sense_tc / dt * (t - t 0 ) where dv sense_tc / dt ~ typically - 5.5 mv/k ( for temperature range ( - 40 c to 150 c). 4.4.3 short to vcc and off - state open - load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off - state. small or no current is delivered by the current sense during the on - state depending on the nature of the short circuit. off - sta te open - load with external circuitry detection of an open - load in off mode requires an external pull - up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. r pu must be selected in order to ensure v out > v olmax in accordance with the following equation: docid027395 rev 1 33/ 46
application information VND7040AJ equation r pu < v pu - 4 i l(off2)min @ 4v 34 46 oci027395 re 1
VND7040AJ maximum demagnetization energy (vcc = 16 v) 5 maximum demagnetization energy (vcc = 16 v) figure 42 : maximum turn off current versus inductance values are generated with r l = 0 . gapgcft01182 0 . 1 1 1 0 1 0 0 0 . 1 1 1 0 1 0 0 1 0 0 0 i ( a) l ( m h) v n d 7040 a j - m ax i mum t urn o f f c urr e n t ve r s u s i ndu c t a n c e v n d 7 0 40 a j - s i ng l e p u l s e r e p e t i t i v e p u l s e t j s t a r t = 10 0 c r e p e t i t i v e p u l s e t j s t a r t = 12 5 c docid027395 rev 1 35/ 46
package and pcb thermal data VND7040AJ 6 package and pcb thermal data 6.1 powersso - 16 thermal data figure 43 : powersso - 16 on two - layers pcb (2s0p to jedec jesd 51-5) figure 44 : powersso - 16 on four - layers pcb (2s2p to jedec jesd 51-7) table 14: pcb properties dimension value board finish thickness 1.6 mm +/ - 10% board dimension 77 mm x 86 mm board material fr4 copper thickness (top and bottom layers) 0.070 mm copper thickness (inner layers) 0.035 mm thermal vias separation 1.2 mm thermal via diameter 0.3 mm +/ - 0.08 mm copper thickness on vias 0.025 mm footprint dimension (top layer) 2.2 mm x 3.9 mm heatsink copper area dimension (bottom layer) footprint, 2 cm 2 or 8 cm 2 36/ 46 docid027395 rev 1
VND7040AJ package and pcb thermal data figure 45 : rthj - amb vs pcb copper area in open box free air condition (one channel on) figure 46 : powersso - 16 thermal impedance junction ambient single pulse (one channel on) e quation: pulse calculation formula z th = r th + z thtp (1 - ) where = t p /t 30 40 50 60 70 80 90 0 2 4 6 8 10 r t hj a m b r t h j a m b gapgcft01183 0 . 1 1 1 0 1 0 0 0 . 00 0 1 0 . 00 1 0 . 0 1 0 . 1 1 1 0 1 0 0 1 0 0 0 z t h ( c / w ) t i m e ( s ) c u = 8 c m 2 c u = 2 c m 2 c u = f oo t p r i n t 4 l ayer gapgcft0 1 184 docid027395 rev 1 37/ 46
package and pcb thermal data VND7040AJ figure 47 : thermal fitting model of a double - channel hsd in powersso -16 the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. table 15: thermal parameters area/island (cm 2 ) footprint 2 8 4l r1 = r7 (c/w) 2.3 r2 = r8 (c/w) 1.8 r3 (c/w) 7 7 7 5 r4 (c/w) 16 6 6 4 r5 (c/w) 30 20 10 3 r6 (c/w) 26 20 18 7 c1 = c7 (w.s/c) 0.00045 c2 = c8 (w.s/c) 0.03 c3 (w.s/c) 0.1 c4 (w.s/c) 0.2 0.3 0.3 0.4 c5 (w.s/c) 0.4 1 1 4 c6 (w.s/c) 3 5 7 18 38/ 46 docid027395 rev 1
VND7040AJ package information 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 powersso - 16 package information figure 48 : powersso - 16 package outline table 16: powersso - 16 mechanical data ref. dimensions millimeters min. typ. max. 0 8 1 0 2 5 15 3 5 15 a 1.70 docid027395 rev 1 39/ 46
package information VND7040AJ ref. dimensions millimeters min. typ. max. a1 0.00 0.10 a2 1.10 1.60 b 0.20 0.30 b1 0.20 0.25 0.28 c 0.19 0.25 c1 0.19 0.20 0.23 d 4.9 bsc d1 2.90 3.50 e 0.50 bsc e 6.00 bsc e1 3.90 bsc e2 2.20 2.80 h 0.25 0.50 l 0.40 0.60 0.85 l1 1.00 ref n 16 r 0.07 r1 0.07 s 0.20 tolerance of form and position aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 40/ 46 docid027395 rev 1
VND7040AJ packa ge information 7.2 powersso - 16 packing information figure 49 : powersso - 16 reel 13" table 17: reel dimensions description value (1) base quantity 2500 bulk quantity 2500 a (max) 330 b (min) 1.5 c (+0.5, - 0.2) 13 d (min) 20.2 n 100 w1 (+2 / -0) 12.4 w2 (max) 18.4 notes: (1) all dimensions are in mm. docid027395 rev 1 41/ 46
package information VND7040AJ figure 50 : powersso - 16 carrier tape table 18: powersso - 16 carrier tape dimensions description value (1) a 0 6.50 0.1 b 0 5.25 0.1 k 0 2.10 0.1 k 1 1.80 0.1 f 5.50 0.1 p 1 8.00 0.1 w 12.00 0.3 notes: (1) all dimensions are in mm. figure 51 : powersso - 16 schematic drawing of leader and trailer tape 0.30 0.05 1.55 0.05 1.60.1 r 0.5 t ypical k 1 k 0 b 0 p 2 2.0 0.1 p 0 4.0 0.1 p 1 a 0 f w 1.75 0.1 se c tion x - x se c tion y - y ref 4.18 ref 0.6 ref 0.5 x x y y gapg2204151242cft 42 46 oci027395 re 1
VND7040AJ package information 7.3 powersso - 16 marking information figure 52 : powersso - 16 marking information engineering samples: these samples can be clearly identified by a dedicated special symb ol in the marking of each unit. these samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by st. st is not liable for any customer usage in production and/o r in reliability qualification trials. commercial samples: fully qualified parts from st standard production with no usage restrictions. gapg0401151415cft 1 2 3 4 5 6 7 8 sp ecial fun c tion digit &: en g inee r ing sample : c omme r cial sample p o w erss o -16 t op vi e w (not in scale) m ar k ing a r ea oci027395 re 1 43 46
order codes VND7040AJ 8 order codes table 19: device summary package order codes tape and reel powersso -16 VND7040AJtr 44/ 46 docid027395 rev 1
VND7040AJ revision history 9 revision history table 20: document revision history date revision changes 19- may -2015 1 initial release. docid027395 rev 1 45/ 46
VND7040AJ important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved 46/ 46 docid027395 rev 1

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